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Processor Datapath and Pipelining

Processor Datapath and Pipelining

Oct 03, 20261 min read

How a processor executes instructions: single-cycle, multi-cycle and pipelined datapaths, hazards and branch prediction.

Area: Computer Engineering

Covered in

  • 5EIB0 Computation II: MIPS Hazards, Branch Predictions, Building a Datapath, An Overview of Pipelining, Data Hazards: Forwarding versus Stalling
  • 5EIB0 Computation II, resit notes: Processor Design (resit) - 5EIB0

Related topics

Instruction Set Architecture · Caches and Memory Hierarchy


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  • Computation II - 5EIB0
  • Processor Design (resit) - 5EIB0
  • Computer Engineering
  • Caches and Memory Hierarchy
  • Instruction Set Architecture

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