Open source, MIT licensed

Design the chip your model needs.

ChipLeap explores the architecture before anyone writes RTL: memory system, external memory, dataflow, compute and process node, each choice explained. Then it generates the hardware, a RISC-V SoC on X-HEEP or AXI4 IP for any host, and checks it down to a routed layout. Or bring RTL of your own: the same flow takes it to a whole chip.

Get started Bring your RTL

pip install chipleap

A rendered die designed by ChipLeap for SmolLM2 135M on the IHP SG13G2 open PDK: SRAM, logic, a GEMV engine and an octal PSRAM interface, bonded into a package. — Rendered to scale from a design ChipLeap produced: SmolLM2 135M on the open IHP 130 nm PDK.

Generates and checks with

X-HEEP
AXI4
IHP SG13G2
cocotb
Verilator
Yosys
SymbiYosys
OpenROAD
LibreLane
KLayout
Fault
MCP

Watch it design a chip

Llama 3.2 1B decoding at 5 tokens per second, within 8 mm² and 400 mW. The agent starts from a bare microcontroller, names what limits it, tries every single change, keeps the best and says why. The floorplan is drawn to scale at every step. This run evaluated 2,154 designs in under 10 seconds.

Start
Start from a bare microcontroller
A CV32E20 at 100 MHz with two 32 KiB banks on IHP 130 nm. The CPU does every multiply itself, and the 642 MiB of weights and KV cache do not fit in a 64 MiB HyperRAM.
0.0097 tokens per second
Decision 1
Move to 65 nm, 200 MHz and LPDDR2
A newer node allows faster clocks and memory interfaces at lower energy. Before this step 100% of the time went to compute.
0.0097 to 0.019 tokens per second, 854 to 327 mJ per token, 3.53 to 2.92 mm², now buildable
Decision 2
Add a GEMV engine
Matrix multiplies dominate and the CPU does them one MAC at a time. Before this step 100% of the time went to compute.
0.019 to 1.70 tokens per second, 327 to 86.2 mJ per token, 2.92 to 3.47 mm²
Decision 3
Move to 28 nm, 400 MHz and LPDDR4X
A newer node allows faster clocks and memory interfaces at lower energy. Before this step 75% of the time went to the accelerator's ports.
1.70 to 3.30 tokens per second, 86.2 to 29 mJ per token, 3.47 to 2.43 mm²
Decision 4
Move to 16 nm, 800 MHz
A newer node allows faster clocks and memory interfaces at lower energy. Before this step 76% of the time went to the accelerator's ports.
3.30 to 6.18 tokens per second, 29 to 27.9 mJ per token, 2.43 to 1.34 mm², meets every target
Decision 5
Switch to LPDDR5
A slower interface can be cheaper in area and energy per bit. Before this step 78% of the time went to the accelerator's ports.
throughput unchanged at 6.18 tokens per second, 27.9 to 22.5 mJ per token, 1.34 to 1.00 mm²
Decision 6
Make the banks 16 KiB
Unused SRAM costs area and leakage. Before this step 78% of the time went to the accelerator's ports.
throughput unchanged at 6.17 tokens per second, 1.00 to 0.97 mm²
No single change lowers the energy further, so the agent stops with a 4 x 8 GEMV engine next to a CV32E20 at 800 MHz in 16 nm, fed by LPDDR5: 6.17 tokens per second at 22.5 mJ per token in 0.97 mm². Its weights now arrive as fast as the accelerator's ports take them in, so more ports would raise the token rate but not lower the energy per token.

One loop, from requirement to RTL

Each stage writes a file the next one reads, so every result can be opened, edited and checked.

DescribeA YAML spec: the model, context and precision; tokens per second, area and power; the nodes and memories you can use.
Sizechipleap require turns the target into bandwidth, MAC rate and capacity, and rules out what cannot deliver.
ExploreThe explainable agent plus a seeded global search: a decision log, a Pareto front, a recommended design.
GenerateAn X-HEEP configuration, the accelerator in SystemVerilog, a register map, a C driver, a testbench, a datasheet.
VerifySimulation against a golden model, cycles against the model, synthesis on IHP SG13G2, X-HEEP's own checks.

The model is checked against the RTL it generates

The accelerator model is the tile schedule the generated hardware runs, so the two can be compared cycle for cycle. These results come from chipleap verify and the test suite on this release.

21random jobs, bit-exact against a golden model

0.0%cycle error, model against RTL, without memory stalls

27X-HEEP templates rendered for the configuration

101MHzclock the routed accelerator reaches on IHP SG13G2 at the slow corner

The routed layout of the 1 x 8 GEMV engine on IHP SG13G2: signal wires on four metal layers under the power grid

And then it is placed and routed

The same accelerator, through LibreLane on IHP SG13G2: placement, clock tree, routing, timing at every corner, DRC and LVS clean. This is the GDS it wrote, drawn in the PDK's layer colours. Its buffers are SRAM macros in silicon, cut to 16 words here.

Standard cells: 31,079
Core area: 0.80mm²
Typical corner: 148MHz
Slow corner, 125 °C: 101MHz

Consistency	Pass design.yaml, RTL wrappers, driver, register map and X-HEEP configuration agree.
Lint	Pass Verilator -Wall reports no warnings.
Simulation	Pass 21 randomized jobs bit-exact; cycle model error 0.0% max without stalls, 3.4% mean with random stalls.
Synthesis	Pass Logic cell area 0.2780 mm² on IHP SG13G2 (model 0.2869 mm², +3%), critical path 3.93 ns, about 228 MHz.
X-HEEP	Pass X-HEEP validated the configuration (1 bank, 0 interleaved) and rendered 27 templates.
Place and route	Pass Placed and routed on IHP SG13G2: 0.796 mm² core at 64% utilisation, 31079 cells; 90 MHz met at the slow corner (about 101 MHz, and about 148 MHz at the typical one); DRC and LVS clean.
Model inputs	Tested Parameter counts of all twelve LLM presets within 2% of their model cards. IHP SG13G2 SRAM area within 2% of the liberty data for every macro size. Accelerator logic area within 3% on average of synthesis across 24 configurations. The C driver plans the same tiles as the model on 6,000 random shapes.

Bring your own RTL

Point ChipLeap at a directory of Verilog or SystemVerilog with cocotb tests and it runs what a tape-out asks of RTL, on open tools and the IHP SG13G2 PDK. Below is what each step reported for examples/uart, a UART transmitter and receiver (8N1) with cocotb tests against a Python reference model, at 100 MHz.

Check the RTL5 steps

LintVerilator 5.052, slang 9.1.0no warnings
Simulationcocotb on Icarus 13.05 of 5 tests pass
CoverageVerilator 5.052line 83.3 %, branch 100 %, toggle 100 %; 2 points no test reaches
FormalSymbiYosys, abc pdrthe design's assertions proved for every cycle
Clock and reset crossingsChipLeap's checker on Yosys's netlist1 crossing, all synchronized (2-flop synchronizer on rx_i); a warning: the reset is released asynchronously

Implement5 steps

SynthesisYosys and ABC on IHP's cells221 cells, 51 flip-flops, 0.0041 mm², critical path 1.01 ns
Place and routeLibreLane (OpenROAD, KLayout), signed off at the slow corner352 cells on a 0.0105 mm² core; 100 MHz met at 125 °C (about 264 MHz there); DRC, LVS and antenna clean
EquivalenceYosys equivalenceRTL to netlist: 74 of 75 proved, the rest equal for 40 cycles; netlist to layout: all 969 points proved
Gate-level simulationcocotb on Icarus 13.0, IHP's cell models5 of 5 tests pass on the routed netlist with SDF delays
ECOnot run here: no eco changes in the project

After the layout4 steps

Design for testOpenROAD scan insertion, Fault 0.9.4 with Quaigh3 chains of 17 flip-flops, 99.2 % stuck-at coverage with 39 patterns, which pass through the chains of the routed netlist
PowerOpenROAD with the project's own tests0.345 mW at the typical corner from the tests' activity (0.947 mW vectorless)
IR dropOpenROAD PDNSim on the routed grid0.52 mV at worst, 0.04 % of 1.2 V
Power intentUPF read and placed by OpenROAD2 domains, PD_RX placed in its own region; 13 signals between them

The chip4 steps

Macrosmacro/v1 packages, checked, their views rewrittenaispice's strongarm, 29.1 x 40.8 um
Chip assemblyLibreLane with IHP's pad ring; bond pads, seal ring and fill in KLayout33 pads on a 1.52 x 1.52 mm die
Timing at the portsOpenSTA through IHP's IO cells, every corner+0.968 ns of setup slack at the slow corner (+6.257 ns at the core's side of the pads)
SignoffIHP's DRC and LVS decks, antenna0 DRC violations, LVS match, 0 antenna violations

# write project.yaml for your RTL
chipleap project init path/to/rtl

# check it, then take it down to the chip
chipleap verify path/to/rtl
chipleap verify path/to/rtl --steps all

Down to a chip

A chip section turns a project into a whole chip: the core, hardened blocks and a pad ring of IHP's IO cells, routed by LibreLane, with bond pads, seal ring and fill, timed at its own ports through the pads, then checked with IHP's own DRC and LVS decks.

The uart_chip layout drawn from its GDS before fill: 33 bond pads and IHP's IO cells around the core, a comparator from aispice in the core, and the seal ring — uart_chip, drawn from the GDS ChipLeap wrote, before fill.

Die with seal ring: 1.52 x 1.52mm
Pads: 33
DRC violations, IHP deck: 0
LVS, IHP deck: match
Setup slack at the ports, slow corner: +0.968ns
Hold slack at the ports, worst corner: +0.118ns

Timed at its ports through IHP's IO cells, the chip's worst path at the slow corner spends 5.4 ns inside the output pad, driving 5 pF: setup slack falls from +6.257 ns at the core's side of the pads to +0.968 ns at the ports.

Every check is IHP's own: the DRC deck on the whole die with its density rules, the LVS deck down to the macros' transistors. How a chip is built and checked.

Analog blocks come from aispice

ChipLeap covers the digital side. Its analog counterpart, aispice, sizes analog blocks on the same PDK, draws their layouts with generators checked by IHP's DRC and LVS decks, and measures their specs before and after extraction. The two hand blocks to each other as macro packages, and both check a package with the same rules before placing it.

aispice The package format

aispiceSizes the block at every corner, draws it, checks DRC and LVS, extracts it.
strongarm.macroGDS, LEF, liberty, Verilog, SPICE, measured specs and the DRC and LVS evidence, named by one macro.toml.
ChipLeapChecks the package, places it in the core and runs LVS down to its transistors.

Ask in plain words. Get a chip.

ChipLeap is an MCP server. Its tools answer architecture questions rather than run single EDA tools, so Claude, Cursor, VS Code or Codex can take a requirement, write the spec, explore, question the bottleneck, then generate and verify the SoC. Every call can be logged and replayed.

claude mcp add chipleap -s user -- chipleap mcp

Claude Desktop, Cursor, VS Code and Codex: docs/mcp.md.

assistant with ChipLeap

Design the smallest chip on the open IHP PDK that runs SmolLM2 135M at two tokens per second.

required_resources(spec)

77 MB read per token: 155 MB/s sustained and 74 MiB resident. At 130 nm only serial memories work: HyperRAM or octal PSRAM, several channels for capacity.

explore_designs(spec, objective="area")

1,767 designs evaluated. The agent added a GEMV engine, doubled the memory channels, moved the weights to octal PSRAM, then made 7 trims to the SRAM, buffers and array, and stopped at the smallest design that still meets the target.

Recommended: CV32E20 at 90 MHz, 32 KiB of SRAM, a 1 x 8 GEMV engine and 2 octal PSRAM channels. 2.22 tokens per second, 42 mW, 3.3 mm², limited by external memory. Shall I generate and verify it?

Yes.

generate_soc(...) verify_soc(...)

All checks pass. 21 randomized jobs bit-exact; cycle counts match the model exactly without memory stalls.

The arithmetic that sets the limit

At batch one, decode reads every weight once per token, so the external memory sets a ceiling no amount of compute can raise. Pick a model and a memory.

Where it fits

Agentic EDA suites from Cadence, Synopsys and Siemens, and startups such as ChipAgents, Chipmind and SigmanticAI, mostly start from a specification or RTL on licensed tools. Workload-to-chip companies such as Architect Labs and Cognichip are closed services. Academic tools such as Timeloop, ZigZag and LLMCompass model accelerators without generating hardware. ChipLeap works on the step before the specification, and hands one over.

Capability	ChipLeap	Agentic EDA suites	Workload-to-chip services	Academic DSE tools
Starts from the workload and its targets	Yes	Spec or RTL	Yes	Yes
Chooses the external memory and checks it can be built at the node	Yes	No	Fixed by the spec	Bandwidth only
Explains every decision in a log you can diff	Yes	Review steps	Not published	Some
Generates an SoC configuration and RTL	X-HEEP SoC or AXI4 IP	RTL	Yes	No
Checks its model against that RTL, cycle for cycle	Yes	Not applicable	Not published	No
Runs locally and free, on open tools and an open PDK	Yes	Licensed	Service	Yes
Also runs the commercial tools and PDK you license	Cadence, Synopsys, Siemens	Their vendor's	Not published	No
Works from any MCP assistant	Yes	Some	No	Rarely

Based on public material as of October 2026. The bottleneck-driven loop follows prior work such as Explainable-DSE (ASPLOS 2024). Full comparison with sources.

Run it on your machine

Python 3.10 or newer. Verilator, Yosys, LibreLane, the IHP PDK and the other tools are optional: chipleap verify uses what it finds and skips the rest with the reason, and chipleap doctor lists it.

View on GitHub Read the docs

# install
pip install chipleap

# write a spec, size it, explore
chipleap init llama.yaml
chipleap require llama.yaml
chipleap explore llama.yaml -o out

# simulate, synthesize, run X-HEEP checks
chipleap verify out

# or bring your RTL, down to the chip
chipleap project init path/to/rtl
chipleap verify path/to/rtl --steps all

Questions

Does it need a commercial EDA licence?

No. Simulation and lint use Verilator, synthesis uses Yosys with sv2v, place and route uses LibreLane, the technology data comes from the IHP SG13G2 open PDK, and X-HEEP's own generator checks the configuration. The model, the explorer and the generators need none of them. If you do have Cadence, Synopsys or Siemens tools, the same checks run on them, on your machine or on a design server, and chipleap tech add reads your own PDK.

Can I use it on RTL I wrote?

Yes. chipleap project init writes a project file for a directory of Verilog or SystemVerilog with cocotb tests, and chipleap verify runs the same checks the generated hardware gets, then the steps after the layout and, with a chip section, the whole chip. docs/projects.md describes the project file and each step.

How accurate is the model?

For the accelerator, the model predicts the generated RTL's cycle count exactly in simulation without memory stalls, and within a few percent with random stalls. Its logic area is within 3% on average of Yosys synthesis on IHP SG13G2, and the synthesized logic runs faster than the clock the model allows there. Memories, CPU and energy rest on technology data that is measured for IHP SG13G2 and scaled from published figures for the other nodes, and reports say which is which. docs/model.md lists every number and its source.

Do I have to use RISC-V or X-HEEP?

No. X-HEEP is the default because it is an open, configurable RISC-V microcontroller from EPFL with a Python configuration API and several chips taped out, and its generator validates what ChipLeap writes. With platform: standalone ChipLeap generates the accelerator alone as AXI4 IP, with a plain C driver, for an Arm, RISC-V or FPGA SoC; its AXI interfaces are simulated bit-exact like the rest.

Can I use my own model or network?

Yes. Any decoder-only transformer can be described by its shape, and other networks as convolutions, depthwise convolutions, matrix multiplies and element-wise operators.

What does the generated accelerator not do yet?

It computes int8 activations against int8, int4 or int2 weights with int32 results. Requantization, activation functions and int4 group scales run on the CPU, and the model counts them there. It has been placed and routed on IHP SG13G2 with clean DRC and LVS, but not taped out.

Has a ChipLeap chip been taped out?

Not yet. The chip on this page passes IHP's DRC deck on the whole die with its density rules, its LVS deck down to the transistors of the macros, antenna checks, timing at every corner through the pads, and the public parts of a shuttle's precheck. Fabrication is the step still missing.

Is it affiliated with EPFL, IHP or any company named here?

No. ChipLeap is an independent open-source project.

Design the chip your model needs.

Watch it design a chip

Start from a bare microcontroller

Move to 65 nm, 200 MHz and LPDDR2

Add a GEMV engine

Move to 28 nm, 400 MHz and LPDDR4X

Move to 16 nm, 800 MHz

Switch to LPDDR5

Make the banks 16 KiB

One loop, from requirement to RTL

The model is checked against the RTL it generates

And then it is placed and routed

Bring your own RTL

Down to a chip

Analog blocks come from aispice

Ask in plain words. Get a chip.

The arithmetic that sets the limit

Where it fits

Run it on your machine

Questions