Desktop app
Schematic, waveforms, specs, history and the chat side by side. Opens a folder of .asc files.
New IC design on an open PDK: corners, layout, DRC and LVS, chips
Design circuits
Design circuits
by describing them.
aispice reads your LTspice schematics, makes the change you ask for, and proves it in simulation on ngspice, LTspice, Xyce or Spectre. Every edit is a diff you can undo. On an open PDK it takes IC blocks down to a layout checked with DRC and LVS.
Free and open source. Linux, Windows and macOS. Your keys, your machine.
Works with the simulators, PDK and models you already use
- ngspice
- LTspice
- Xyce
- Spectre
- IHP SG13G2
- KLayout
- Magic
- xschem
- Claude
- GPT
- Gemini
- Ollama
- Claude Code
- Cursor
Edit
Changes you can review, not files rewritten behind your back.
The agent edits with typed operations: set a value, add a part, connect two pins. aispice places and routes them so the schematic stays readable in LTspice, outlines what changed, and keeps a snapshot for one-click undo.
- Wires never short two nets
- Ask before every edit, or apply and undo
- Netlists identical to LTspice's own
Verify
Proof, not claims.
Write your requirements once as a spec table: corner frequency, gain, phase margin, ripple. After every change the agent simulates and checks each row, and tells you when one fails, with the margin.
- Bandwidth, margins, overshoot, settling, THD and more
- Waveforms with cursors in the app
aispice checkfails a CI job when a spec does
Size
Values from an optimizer, robustness from Monte Carlo.
The model picks what to tune and the ranges; a numerical optimizer searches them with the simulator in the loop and snaps the answer to E24 values. A Monte Carlo run with real tolerances then says how many builds would pass.
- Sweeps, worst-case corners and yield
- Bias point of every transistor: region, gm, gm/Id
- Poles and zeros, f0 and Q
IC design
Transistor-level blocks on an open PDK.
Register IHP SG13G2 once and a project simulates with the PDK's own device models on ngspice or Xyce. The agent sizes transistors by gm/Id from tables it builds, starts from templates checked at every corner, and checks each spec across process, temperature, supply and mismatch.
- Six templates, from a current mirror to an LDO, at every corner of their set
- The worst corner named for each spec; mismatch Monte Carlo on IHP's statistical models
- Noise, PSRR and CMRR, input or output referred
aispice check two_stage.asc --process tt,ss,ff,sf,fs --temp=-40,27,125
all 3 specs pass at all 15 corners PASS gain: 51.1dB worst at fs/125C (>= 48dB) pass, margin +6.5% PASS gbw: 15.21MHz worst at ss/125C (>= 13MHz) pass, margin +17.0% PASS pm: 57° worst at ff/-40C (>= 52°) pass, margin +9.6%
Layout
From schematic to a checked layout.
Generators draw the block with IHP's own pcells: matched devices in common-centroid or interdigitated units, dummies and guard rings. IHP's KLayout decks check DRC and LVS, Magic extracts the parasitics, and every spec is reported before and after layout. When a check fails, the agent changes the generator's parameters and draws again; it never edits the GDS.
- Two-stage op-amp, drawn
- 22.2 x 44.1um
- Devices and dummies
- 9 + 8
- Draw, DRC, LVS
- 1.1 + 2.5 + 2.5s
- DRC and LVS, IHP's decks
- clean
After layout, the five-transistor OTA's unity-gain frequency goes from 113.7 to 105.2 MHz and its phase margin from 84.5 to 82.5 degrees, rerun on the extracted netlist.
Mixed signal
Analog and logic in one simulation.
A project declares Verilog-A models and Verilog to co-simulate. aispice builds them itself with OpenVAF and Verilator, runs the result in a sandbox, and ngspice simulates the transistors and the logic together. Above the block, the budget tool splits a target into block specs with every equation, and the trim check finds the code that brings a trimmed block into range at every corner and mismatch sample.
- Behavioural models and co-simulated Verilog, sandboxed
- ADC front-end and LDO budgets written as spec tables
- Every trim code at every corner and sample
budget: a 10-bit ADC front end, ENOB 9.5, 50 MS/s
sampling capacitor (each side) = 207.9fF OTA gain-bandwidth = 404.5MHz OTA DC gain in dB = 72.25dB OTA input noise density = 11.2nV/rtHz
Chips
Blocks for chips, with ChipLeap.
A finished block becomes a macro package: GDS, LEF, liberty, a Verilog model, the SPICE netlist, specs measured at every corner and the DRC and LVS evidence. aispice and its digital counterpart, ChipLeap, check a package with the same rules. aispice assembles analog-on-top chips in IHP's pad ring with ChipLeap's hardened logic inside; ChipLeap places aispice's blocks in its digital chips.
- Die
- 1.04 x 1.04mm
- Pads
- 16
- DRC, all four decks
- clean
- LVS, to the counter's cells
- clean
Every change is simulated before it reaches you.
660/660
schematics netlisted exactly as LTspice does
49/49
of IHP's xschem test benches netlisted line for line as xschem does
23
reference circuits passing their specs, 6 of them IC blocks at every corner
5
layout generators, DRC and LVS clean on IHP's own decks
Use it
One engine, wherever you work.
Command line
Simulate, lint, draw a netlist as a schematic, and check specs in CI.
aispice check amp.ascMCP server
The same tools inside Claude Code, Cursor, Codex or Claude Desktop.
claude mcp add aispice -- aispice mcpPrivate by default
Runs on your machine.
No account, no sign-up, no telemetry. The only requests go to the model provider you choose, and with a local model through Ollama nothing leaves your computer. Keys stay in the operating system's keychain, and the agent's tools are confined to the folder you opened.
Do I need LTspice?
No. ngspice works out of the box. When LTspice is installed, aispice uses its parts library and can show each edit in LTspice.
Which models work?
Anthropic, OpenAI, Google, OpenRouter, Ollama, or any OpenAI-compatible endpoint. Frontier models do the best multi-step design work; small local models handle reading, editing and simulating.
Can it use my PDK?
Yes. Register an installed PDK with aispice pdk add (IHP SG13G2 from IHP-Open-PDK first): simulations load its device models on ngspice or Xyce, and layouts use its pcells and its DRC and LVS decks. A licensed PDK works through Spectre on your own server over SSH, and its model files never leave it.
Does it do layout?
For IC blocks on IHP SG13G2, yes: five generators (current mirror, differential pair, five-transistor OTA, two-stage op-amp, StrongARM comparator) draw with the PDK's pcells, then IHP's decks check DRC and LVS and Magic extracts the parasitics. Board layout is not part of aispice.
How does it work with ChipLeap?
ChipLeap is the digital counterpart: RTL to a chip with a pad ring. The two exchange hardened blocks as macro packages, checked by both with the same rules, so an aispice comparator can sit in a ChipLeap chip and ChipLeap's logic in an aispice chip.
Is it affiliated with Analog Devices?
No. aispice is an independent open-source project. LTspice is a trademark of Analog Devices, Inc.
Start with the circuit you have.
Open a folder of LTspice schematics and ask for the first change.
cargo install --locked --git https://github.com/danieltyukov/aispice aispiceThe command line tool from source, with Rust 1.88 or newer. Every release is on GitHub.