FPGA (resit) - 5EIB0

Resit notes for Computation II - 5EIB0

• Topics: Hardware Description Languages and FPGAs

ELI5: The best way to start learning Verilog - YouTube
Detailed syntax: Verilog HDL Basics - YouTube

Abstraction levels

Switch (not supported by Vivado synthesizer)

Gate

Data flow

Behavioral

Data types

• Net: wire, tri (three-state logic), supply0, supply1
• Variable: reg, integer, (real, time, realtime - no synthesis)
  

Blocking vs Nonblocking

Blocking: combinational logic → statements executed sequentially
Nonblocking: sequential logic → statements executed in parallel

Guidelines

1. Sequential logic: nonblocking
2. Latch: nonblocking
3. Combinational: blocking
4. Sequential + Combinational (not recommended): nonblocking
5. 4 is not recommended
6. No assigments to a var in > 1 always block
7. Use $strobe for nonblocking
8. Don’t use #0 delay assignments

Finite State Machine (resit) - 5EIB0

Motivation

• Prototyping of processors before manufacturing → soft core processor
• Optimize for application driven >< multi purpose like MCU → Application Specific IC (ASIC)
• Can add peripherals
• Open-source → add instructions

Definition

• Blocks of programmable digital logic

Properties

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Related Concepts

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